Semiconductor device with wiring layer of low resistance

ABSTRACT

A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

BACKGROUND OF THE INVENTION

1. 1. Field of the Invention

2. The present invention relates to a semiconductor device having apolycide wiring layer in which a high melting point metal silicide layeris laminated on a polysilicon layer. More particularly, the presentinvention relates to a semiconductor device and a method ofmanufacturing the same, in which a wiring layer resistance of a polycidewiring layer is reduced for realization of fine patterns and high speedoperation in the semiconductor device.

3. 2. Description of the Related Art

4. With the high integration in a semiconductor device, it is aimed fora wiring layer between semiconductor elements or between the element andan electrode to have a fine and thin structure. For example, it isrequired to reduce the wiring layer width from the range of 200 to 250nm to the range of 40 to 100 nm. Therefore, the increase of wiringresistance with the formation of the fine and thin wiring layer can notbe ignored, and the decrease of the wiring layer resistance is required.

5. For example, when the wiring layer is applied to a word line of asemiconductor memory device, the access time of the memory devicebecomes long, if the wiring layer resistance is large. For this reason,the length of the word line can not be made longer than a predeterminedvalue. As a result, the number of memory elements connectable with theword line can not be increased.

6. In order to solve the above problem, one word line is divided into aplurality of blocks, and a word line drive signal is supplied to theword line in each block through a buffer. However, in this method, thereis a problem in that the memory chip size becomes large.

7. In order to achieve the reduction of the wiring layer resistance, itcould be considered that metal, especially, high melting point metal isused as a material of the wiring layer. However, this technique can notbe applied, when it is necessary to use polysilicon as the wiring layermaterial, like the wiring layer used as a gate electrode in a MOStransistor of the semiconductor device. Therefore, as one approach tomake the wiring layer resistance of the polysilicon layer low, apolycide wiring layer is conventionally proposed.

8. The polycide wiring layer structure is shown in FIGS. 1A and 1B as aplan view and a cross sectional view, respectively. A polysilicon layer204 is formed above a silicon substrate 201 on which a trench separationinsulating film 202 and a gate insulating film 203 have been formed. Ahigh melting point metal silicide 205 is laminated on the polysiliconlayer 204. The polysilicon layer 204 and the high melting point metalsilicide layer 205 are patterned into a predetermined pattern to form apolycide wiring layer 206. Thus, it is realized to make the wiring layerresistance low by use of a low sheet resistance of the high meltingpoint metal silicide.

9. In such a polycide wiring layer, impurity ions, e.g., phosphorus ionsare doped into the polysilicon 204 to realize the low resistance of thepolysilicon 204. Also, the high melting point metal silicide layer 205is formed by a CVD method. The high melting point metal silicide iscomposed of a lot of needle-shape crystals formed on the polysiliconsurface on the formation of the high melting point metal silicide layer205. A thermal annealing process is applied to the needle-shape crystalssuch that the crystals grow. Thus, grains or particles 205G with arequired grain diameter are obtained. The polycide layer formed in thisway is etched and patterned into a requested pattern using thephotolithography technique, so that the polycide wiring layer 206 iscompleted.

10. By the way, the inventor studied such a polycide wiring layer.Consequently, it was discovered that the polycide wiring layer was notmade low in resistance. The inventor paid attention to tungsten silicide(WSi) as the high melting point metal silicide, especially, the grainsof tungsten silicide and observed them with an electron microscope. Asthe result of observation, the grain size or grain diameter of the grainwas small rather than the film thickness of the WSi layer and the filmwidth of the WSi layer. Also, the grains were formed in the state inwhich the grains were arranged in the film thickness direction of theWSi layer and the width direction of the WSi layer.

11. That is, the composition ratio of tungsten (W) and silicon (Si) inthe formation of the WSi layer would be as large as 1:2.5, from thecondition in the formation of the WSi layer. Also, a thermal annealingprocess after the formation of the WSi layer was carried out under thecondition of the temperature equal to or lower than 900° C. andannealing time of about 60 minutes. Therefore, it is inferred that Siatoms are deposited in the boundary between the grains, and the Si atomsfunction to hinder the growth of the grain.

12. Therefore, in an example shown in FIGS. 1A and 1B, Si atoms aredeposited in the interface 205B between the grains 205G and thedeposited Si atoms function to obstruct current flow between the grains.As a result, the sheet resistance of WSi layer becomes large. Also, whenthe polycide wiring layer is patterned, the wiring layer has the highresistance. It should be noted that the grain size or diameter means amaximum of the grain diameters in the present invention.

13. It should be noted that it is described in Japanese Laid Open PatentApplication (JP-A-Heisei 7-283217) that the wiring layer resistanceincreases when the wiring layer has the width smaller than the grainsize of titanium silicide (TiSi) in a titanium silicide layer. This doesnot correspond to the above studying by the inventor. This would bebecause of the difference between the reference and the presentinvention in manufacturing method. That is, in the reference, a thermalannealing process is carried out to form the TiSi layer after a titaniumlayer is deposited on a polysilicon layer. On the other hand, in thepresent invention, the WSi layer is formed on the polysilicon layer bythe CVD method, to be described later.

14. Regardless of the cause, when the WSi grain size is smaller than thewidth and film thickness of the wiring layer, it is difficult to reducethe wiring layer resistance, as described above. Also, when the WSilayer is formed using a sputtering method, the grain diameter of the WSigrain is small. In order to increase the grain diameter of the WSigrain, it is necessary to perform the annealing process at a hightemperature for a long time. However, when a gate wiring layer of thesemiconductor device is formed of WSi, it is not possible to perform theannealing process for the long time, since the annealing process affectsthe diffusion layers of the source and drain.

SUMMARY OF THE INVENTION

15. An object of the present invention is to provide a semiconductordevice and a method of manufacturing the same, in which a polycidewiring layer which is composed of a high melting point metal silicidehaving a low resistance.

16. In order to achieve an aspect of the present invention, asemiconductor device includes a polysilicon film formed directly orindirectly on a semiconductor substrate, and a refractory metal silicidefilm formed on the polysilicon film. The refractory metal silicide filmcomprises grains of refractory metal silicide. At least a portion of thegrains has a maximum grain diameter equal to or larger than at least oneof a film thickness of the refractory metal silicide film and a filmwidth of the refractory metal silicide film.

17. It is preferable that the film thickness of the refractory metalsilicide is in a range of 100 to 150 nm, the film width of therefractory metal silicide is in a range of 40 to 250 nm, and the maximumgrain diameter is in a range of 150 to 200 nm.

18. The refractory metal silicide may be tungsten silicide (WSi). Also,it is preferable that the refractory metal silicide has a sheetresistance in a range of 2 to 4 Ω/□.

19. When the semiconductor device includes a gate insulating film formedon the semiconductor substrate, and the refractory metal silicide isformed on the gate insulating film, the polysilicon film and therefractory metal silicide preferably function a gate electrode of a MOStransistor and a wiring layer.

20. The semiconductor device may further include a coverage film formedon the refractory metal silicide, for suppressing growth of the grainsin a direction of the film thickness. In this case, the coverage filmmay be a silicon oxide film.

21. In order to achieve another aspect of the present invention, amethod of manufacturing a semiconductor device, includes:

22. forming a polysilicon film formed directly or indirectly on asemiconductor substrate;

23. forming a refractory metal silicide film formed on the polysiliconfilm;

24. performing heat treatment such that at least a portion of grains ofthe refractory metal silicide film has a maximum grain diameter equal toor larger than at least one of a film thickness of the refractory metalsilicide film and a film width of the refractory metal silicide film;and

25. patterning the polysilicon film and the refractory metal silicideafter the heat treatment.

26. The refractory metal silicide film may be a tungsten silicide film.In this case, the step of forming a refractory metal silicide filmincludes reacting tungsten and silicon with a composition ratio in arange of 1:2.0 to 1:2.2.

27. Also, the step of performing heat treatment may include performing arapid thermal annealing method at a temperature equal to or higher than950° C. for a time equal to or shorter than 60 seconds. The step ofperforming a rapid thermal annealing method may include performing therapid thermal annealing method at a temperature in range of 950 to 1000°C. for a time substantially equal to 60 seconds. The step of performinga rapid thermal annealing method may include performing the rapidthermal annealing method at a temperature in range of 1000 to 1100° C.for a time substantially equal to 15 seconds.

28. The step of performing heat treatment may include performing a rapidthermal annealing method such that the refractory metal silicide filmhas a sheet resistance in a range of 2 to 4 Ω/□.

29. The step of performing heat treatment may include performing a rapidthermal annealing method such that the maximum grain diameter is in arange of 150 to 200 nm.

30. In order to achieve still another aspect of the present invention, asemiconductor device includes a polysilicon film formed directly orindirectly on a semiconductor substrate, and a refractory metal silicidefilm formed on the polysilicon film to have a sheet resistance in arange of 2 to 4.

BRIEF DESCRIPTION OF THE DRAWINGS

31.FIGS. 1A and 1B are a plan view and a cross sectional view of aconventional polycide wiring layer, respectively;

32.FIG. 2 is a cross sectional view of a semiconductor device toillustrate a film forming process in a method of manufacturing asemiconductor device of the present invention;

33.FIG. 3 is a schematically perspective view of the semiconductordevice to illustrate a thermal annealing process of the method ofmanufacturing of the present invention;

34.FIG. 4 is a diagram showing a relation of annealing temperature andgrain diameter;

35.FIG. 5 is a diagram showing a relation of grain diameter and sheetresistance;

36.FIG. 6 is a diagram showing a relation of annealing condition andsheet resistance;

37.FIG. 7 is a perspective view of the semiconductor device toillustrate a polycide wiring layer manufactured in the presentinvention;

38.FIGS. 8A and 8B are a plan view and a cross sectional view of thesemiconductor device shown in FIG. 6, respectively;

39.FIG. 9 is a diagram to illustrate the film forming process accordingto a second embodiment of the present invention; and

40.FIG. 10 is a diagram to illustrate the thermal annealing processaccording to the second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

41. Next, a semiconductor device of the present invention will bedescribed below in detail with reference to the attached drawings.

42.FIG. 2 is a cross sectional view of the semiconductor deviceaccording to the first embodiment of the present invention in themanufacturing process.

43. Referring to FIG. 2, a trench (concave structure) with apredetermined depth is formed in an element separation region on asilicon substrate 101. An insulation material film such as a siliconoxide film is embedded in the trench to form a trench separationinsulating film 102. Also, a gate oxide film 103 of a silicon oxide filmis formed on the surface of the silicon substrate 101 in an elementforming region which is segmented by the trench separation insulatingfilm 102. Subsequently, a polysilicon film 104 is formed on the gateoxide film 103 by an LP-CVD method to have the film thickness of 100 nm.The polysilicon film 104 is doped with phosphorus ions to decrease theresistance. Then, a tungsten silicide (WSi) film 105 is formed on thepolysilicon film 104 by a CVD method to have the film thickness of 150nm. The film forming condition is as follows: a mixture gas ofWF₆/SiH₂Cl₂ is used, the temperature is in a range of 500 to 550° C.,and the pressure is in a range of 80 to 100 Pa.

44. As a result, the WSi layer is formed to have the composition ratioof W and Si in a range of 1:2.0 to 1:2.2. The WSi layer is formed to becomposed of a lot of needle-shaped crystals which are directed from thesurface of the polysilicon film 104 toward an upper portion, as shown inthe figure.

45. Next, as show by a perspective view of FIG. 3, a thermal annealingprocess is carried out to the WSi layer 105 to grow the needle crystals105G so that grains with large grain diameters are grown. The thermalannealing process is carried out at the temperature in a range of 950°C. to 1100° C. for 15 to 60 seconds in a nitrogen ambience by a rapidthermal annealing method (RTA) using a lamp annealing. Through thethermal annealing process, the grains of the WSi layer 105G are grown tohave the grain diameters of 150 nm to 200 nm as the grains 106G.

46. The relation between the annealing temperature and the graindiameters of the grains in the WSi layer is shown in FIG. 4. The resultshown in FIG. 4 is obtained through the experiment by the inventor.Because the absolute values of the sizes of the needle crystals aredifferent in the initial stage of the formation of the WSi layer,specific values are not indicated. However, it could be understood thatthe grain size becomes large as the thermal annealing temperature isincreased. Also, it is confirmed that the sheet resistance of the WSilayer is reduced with the growth of the grain size, as shown in FIG. 5.

47. Three thermal annealing processes were carried out to samples, toverify the characteristics of FIGS. 4 and 5. They were a furnaceannealing (FA) process at the temperature in a range of 800° C. to 900°C. for 10 minutes, a rapid thermal annealing (RTA) process at thetemperature in a range of 900° C. to 1000° C. for 60 seconds, and theRTA process in a range of 1000° C. to 1100° C. for 15 seconds. FIG. 6shows the experiment result for the sheet resistances of the WSi layers.As seen from the figure, the WSi layer with low sheet resistance isobtained when the rapid thermal annealing (RTA) process is carried outat higher temperature for a short time.

48. In the present invention, the WSi layer is obtained to have thesheet resistance of 2 to 4 Ω/□. For this purpose, the annealingcondition is adopted of the rapid thermal annealing (RTA) temperatureequal to or higher than 950° C. for 60 seconds, or the RTA time equal toor higher than 1000° C. for 15 seconds. If the annealing temperature isthe same, as the annealing time becomes longer, the grain size becomeslarger, so that the sheet resistance becomes low. Also, when the rapidthermal process is performed, any influence to the source and draindiffusion layers can be suppressed to the minimum.

49. In this way, as shown in FIG. 7, the polycide layer in which thepolysilicon layer 104 and the WSi layer 106 are laminated is selectivelyetched to have the width of 100 nm, so that a gate electrode 107 ofpolycide is formed.

50. For example, when the present invention is applied to a DRAM as thesemiconductor device having a MOS transistor in a memory cell, the gateelectrode 107 functions as a word line wiring layer. Therefore, the wordline wiring layer 107 is formed as the polycide wiring layer having thepolycide structure. Thus, as show in FIGS. 8A and 8B as a plan view anda side view, the WSi layer 106 of the word line 107 has the filmthickness of 100 nm to 150 nm and the film width of 100 nm. The WSigrains 106G have the grain diameter of 150 nm to 200 nm. The graindiameter of the WSi grain is larger than the film thickness and the filmwidth of the WSi wiring layer 106. Thus, a distance from an interface106B between the grains to another interface 106B in the word line 107is elongated. In this manner, it is sufficient that the grain diametersof a portion of the WSi grains are larger at least one of the filmthickness direction of the word line 107 and the film width directionthereof 106B becomes large. Thus, the number of interfaces 106B whichcrosses in the width direction of the WSi layer 106 is reduced. Also, itcan be restrained that the wiring layer resistance is increased due toSi atoms deposited in the interface 106B. As a result, it becomespossible to reduce the resistance of the word line wiring layer 107.

51. Impurity diffusion layers are formed as source and drain regions onthe surface of a silicon substrate, after the word line wiring layer 107is formed. An interlayer insulating film is formed on the surface of thesilicon substrate 101, and then contact holes are formed to connect tothe impurity diffusion layers. A semiconductor device such as a DRAM iscompleted through the above well known processes. However, because thesubsequent process is little relation with the present invention, thedescription of the subsequent process will be omitted.

52. According to the first embodiment, the WSi grains with the grainsize equal to or larger than 150 nm to 200 nm can be formed under thefollowing film formation conditions such as the reaction in thecomposition ratio of W and Si in a range of 1:2.0 to 1:2.2, and thesubsequent rapid thermal annealing process at the temperature equal toor more than 950° C. for 60 seconds. Therefore, even when the polycidewiring layer is requested to have the film thickness of 100 to 150 nmand the film width of 100 nm, it is possible to form a wiring layer inwhich the WSi grain size is larger than at least one of the filmthickness of the WSi wiring layer and the film width thereof. In thisway, the polycide wiring layer with a low wiring layer resistance can berealized, so that the semiconductor device with a high gate density canbe realized. Also, the number of memory cells connectable with a singleword line can be increased. Further, when one word line is divided intoa plurality of blocks, the number of blocks can be decreased. Therefore,the number of buffers for driving the word line can be reduced such thatthe chip size of the memory can be reduced.

53. FIGS. 9 and 10 are cross sectional views of the semiconductor deviceaccording to the second embodiments of the present invention toillustrate the processes of forming the WSi layer and carrying out athermal annealing. It should be noted that the same components as thoseshown in the first embodiment are allocated with the same referencenumerals as those in the first embodiment, respectively.

54. In the second embodiment, as shown in FIG. 9, the trench separationinsulating film 102 is formed on the silicon substrate 101, like thefirst embodiment. The gate oxide film 103 composed of the silicon oxidefilm is formed on the surface of the silicon substrate 101 in theelement forming region segmented by the trench separation insulatingfilms. Then, the polysilicon film 104 with phosphorus ions doped todecrease the resistance is formed on the gate oxide film by the LP-CVDmethod to have the film thickness of 100 nm, like the first embodiment.Subsequently, the WSi layer 105 is formed on the polysilicon film 104 bythe CVD method to have the film thickness of 150 nm. The film formingcondition at this time is as follows: the temperature is in a range of500 to 550° C. and the pressure is in a range of 80 to 100 Pa, using amixture gas of WF₆/SiH₂Cl₂. Thus, the WSi layer 105 having thecomposition ratio of W and Si in a rage of 1:2.0 to 1:2.2 is formed. TheWSi grains 105 are formed as many needle crystals 105G directed upwardfrom the surface of the polysilicon film 104, as shown in FIG. 9.

55. Next, a silicon oxide film 108 is formed on the surface of the WSilayer 105 to have the film thickness of about 100 nm such that thesilicon oxide film 108 covers the surface of the WSi layer 105. Then,like the first embodiment, a thermal annealing process is carried out tothe WSi layer 105 so that the needle crystals 105G are grown to thegrains 106G with a larger grain diameter, as shown in FIG. 10. Thus, theWSi layer 106 composed of the grains 106G is formed. In this thermalannealing process, a rapid thermal annealing (RTA) by use of a lampannealing is performed at the temperature in a range of 950° C. to 1100°C. for 15 to 60 seconds in the nitrogen ambience. The grain diameter ofthe grains 106G of the WSi layer 106 are grown to be 150 nm 200 nmthrough the thermal annealing process. Subsequently, although beingomitted in the figure, the silicon oxide film 108, the WSi layer 106 andthe polysilicon film 104 are collectively patterned into a desiredpattern so as to form the polycide wiring layer having the film width of100 nm.

56. In the second embodiment, it is possible to form the WSi layercomposed of the grains having equal to or larger than 150 nm to 200 nm.When the polycide wiring layer should be formed to have 100 to 150 nmand the film width of 100 nm, the WSi grain can be formed to be largerthan at least one of the film thickness of the WSi layer and the filmwidth thereof. Thus, the polycide wiring layer having a low wiring layerresistance can be realized such that the semiconductor device with ahigh integration density can be realized.

57. Also, in the second embodiment, since the WSi layer 105 is coveredby the silicon oxide film 108 in the thermal annealing process, the WSigrain growth to the thickness direction of the WSi layer is restrained.On the contrary, the WSi grain growth to the plane direction of the WSilayer is promoted. Therefore, the grain size of the grains 106G in theplane direction becomes larger in the annealed WSi layer 106.Especially, the present invention can be applied to the polycide wiringlayer when the polycide wiring layer width is restricted.

58. In the present invention, the grain diameter of each grain of a highmelting point metal silicide or refractory metal silicide of thepolycide wiring layer such as WSi in all the directions may be notlarger than one of the film thickness of the refractory metal silicideand the film width thereof. That is, it is preferable that the graindiameters of all the grains of the high melting point metal silicide arelarger than the film thickness and the film width. However, because itis difficult that the grain diameters of all the grains actually meetssuch a condition. Therefore, if at least one of the grains of the highmelting point metal silicide meets the above condition, the advantage ofthe present invention can be attained.

59. In he above embodiments, the width of the WSi wiring layer isdescribed to be 100 nm. However, the present invention is not limited tothis. It is confirmed that the effect of the present invention can beattained for the wiring layer width of 40 nm to 250 nm.

60. As described above, according to the present invention, which atleast one grain of the high melting point metal silicide laminated onthe polysilicon layer in the polycide wiring layer is formed to have thegrain size larger than at least one of the film thickness of the highmelting point metal silicide and the film width thereof. The state inwhich the interface between the grains of the high melting point metalsilicide is continuous in the direction of the film thickness or thefilm width is increased. For this reason, even if Si atoms are generatedat the interface between the grains, the increase of the wiring layerresistance due to the Si atoms can be restrained. As a result, it ispossible to form the polycide wiring layer having a low resistance.Especially, when the present invention is applied to the WSi layer, Wand Si are reacted in the composition ratio in a rage of 1:2.0 to 1:2.2,and then a thermal annealing process is carried out at the temperatureequal to or higher than 950° C. for 60 seconds by the RTA method. Thus,it is possible to form the WSi layer whose grain has the grain sizeequal to or more than 150 nm to 200 nm. When the polycide wiring layeris formed to have the film thickness in a range of 100 to 150 nm and thefilm width in rage of 40 to 250 nm, the polycide wiring layer can beformed such that the WSi grain size is larger than at least one of thefilm thickness of the WSi layer and the film width. Thus, thesemiconductor device with a high integration density and a high speedoperation can be realized.

What is claimed is:
 1. A semiconductor device comprising: a polysiliconfilm formed directly or indirectly on a semiconductor substrate; and arefractory metal silicide film formed on said polysilicon film, andwherein said refractory metal silicide film comprises grains ofrefractory metal silicide, and at least a portion of said grains has amaximum grain diameter equal to or larger than at least one of a filmthickness of said refractory metal silicide film and a film width ofsaid refractory metal silicide film.
 2. A semiconductor device accordingto claim 1 , wherein said film thickness of said refractory metalsilicide is in a range of 100 to 150 nm, said film width of saidrefractory metal silicide is in a range of 40 to 250 nm, and saidmaximum grain diameter is in a range of 150 to 200 nm.
 3. Asemiconductor device according to claim 1 , wherein said refractorymetal silicide is tungsten silicide (WSi).
 4. A semiconductor deviceaccording to claim 1 , wherein said refractory metal silicide has asheet resistance in a range of 2 to 4 Ω/□.
 5. A semiconductor deviceaccording to claim 1 , further comprising a gate insulating film formedon said semiconductor substrate, said refractory metal silicide beingformed on said gate insulating film, and wherein said polysilicon filmand said refractory metal silicide function a gate electrode of a MOStransistor and a wiring layer.
 6. A semiconductor device according toclaim 1 , further comprising a coverage film formed on said refractorymetal silicide, for suppressing growth of said grains in a direction ofsaid film thickness.
 7. A semiconductor device according to claim 6 ,wherein said coverage film is a silicon oxide film.
 8. A method ofmanufacturing a semiconductor device, comprising: forming a polysiliconfilm formed directly or indirectly on a semiconductor substrate; forminga refractory metal silicide film formed on said polysilicon film;performing heat treatment such that at least a portion of grains of saidrefractory metal silicide film has a maximum grain diameter equal to orlarger than at least one of a film thickness of said refractory metalsilicide film and a film width of said refractory metal silicide film;and patterning said polysilicon film and said refractory metal silicideafter said heat treatment.
 9. A method according to claim 8 , whereinsaid refractory metal silicide film is a tungsten silicide film.
 10. Amethod according to claim 9 , wherein said step of forming a refractorymetal silicide film includes reacting tungsten and silicon with acomposition ratio in a range of 1:2.0 to 1:2.2.
 11. A method accordingto claim 8 , wherein said step of performing heat treatment includes:performing a rapid thermal annealing method at a temperature equal to orhigher than 950° C. for a time equal to or shorter than 60 seconds. 12.A method according to claim 11 , wherein said step of performing a rapidthermal annealing method includes: performing said rapid thermalannealing method at a temperature in range of 950 to 1000° C. for a timesubstantially equal to 60 seconds.
 13. A method according to claim 11 ,wherein said step of performing a rapid thermal annealing methodincludes: performing said rapid thermal annealing method at atemperature in range of 1000 to 1100° C. for a time substantially equalto 15 seconds.
 14. A method according to claim 8 , wherein said step ofperforming heat treatment includes: performing a rapid thermal annealingmethod such that said refractory metal silicide film has a sheetresistance in a range of 2 to 4 Ω/□.
 15. A method according to claim 8 ,wherein said step of performing heat treatment includes: performing arapid thermal annealing method such that said maximum grain diameter isin a range of 150 to 200 nm.
 16. A method according to claim 8 , furthercomprising forming a gate insulating film on said semiconductorsubstrate, said refractory metal silicide being formed on said gateinsulating film, and wherein said polysilicon film and said refractorymetal silicide function a gate electrode of a MOS transistor and awiring layer.
 17. A method according to claim 8 , further comprisingforming a coverage film on said refractory metal silicide to suppressgrowth of said grains in a direction of said film thickness, before saidheat treatment.
 18. A method according to claim 17 , wherein saidcoverage film is a silicon oxide film.
 19. A method according to claim 8, wherein said patterning includes patterning said polysilicon film andsaid refractory metal silicide film to have said film width in a rangeof 40 to 250 nm.
 20. A semiconductor device comprising: a polysiliconfilm formed directly or indirectly on a semiconductor substrate; and arefractory metal silicide film formed on said polysilicon film to have asheet resistance in a range of 2 to
 4. 21. A semiconductor deviceaccording to claim 20 , wherein said refractory metal silicide filmcomprises grains of refractory metal silicide, a film thickness of saidrefractory metal silicide is in a range of 100 to 150 nm, a film widthof said refractory metal silicide is in a range of 40 to 250 nm, and amaximum grain diameter of said grains is in a range of 150 to 200 nm.22. A semiconductor device according to claim 21 , wherein saidrefractory metal silicide is tungsten silicide (WSi).
 23. Asemiconductor device according to claim 20 , wherein said refractorymetal silicide film comprises grains of refractory metal silicide, andat least a portion of said grains has a maximum grain diameter equal toor larger than at least one of a film thickness of said refractory metalsilicide film and a film width of said refractory metal silicide film.